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A FLEXIBLE PLATFORM FOR NETWORK PROCESSING

A FLEXIBLE PLATFORM FOR NETWORK PROCESSING

A FLEXIBLE PLATFORM FOR NETWORK PROCESSING

Kurtis B. Kredo II, Dr. Albert A. Liddicoat, Dr. Hugh M. Smith, Dr. Phillip L. Nico

California Polytechnic State University, San Luis Obispo

1 Grand Avenue, EE Department San Luis Obispo, CA 93407

United States

[email protected], (aliddico, husmith, and pnico)@calpoly.edu

ABSTRACT

Much of the current research in computer networks

focuses on providing increasing levels of functionality at

very high bandwidths. Traditional implementations using

application specific integrated circuits (ASICs) can

process data very quickly, but do not allow modification

when protocols or algorithms change. Software-based

implementations provide the ability to change

functionality very easily, but often can not support high

bandwidths. The third generation Cal Poly Intelligent

Network Interface Card (CiNIC), presented in this paper,

combines the speed of hardware implementation with the

flexibility of a software-based system by using field

programmable gate arrays (FPGAs) and a hardcore

processor to perform network protocol processing.

Utilizing the CiNIC within a network device allows

developers and researchers to implement additional

functionality in various ways. The CiNIC Platform has

been developed for flexibility and may be used for a

broad range of research and development projects

including hardware/software co-design, embedded

systems, and distributed systems.

KEY WORDS

Network Interfaces, Computer Networks, Protocol

Offloading, Reprogrammable Devices, Intelligent NIC

1. Introduction

Current advances in fiber optic technology have made

large amounts of bandwidth available in computer

networks as users have placed increasing demands upon

network devices [1, 2, 3]. Providing hardware that can

utilize these speeds has often been the sole domain of

application specific integrated circuits (ASICs).

However, ASICs are not flexible enough to be used

within network devices that must be updated often or

within systems that change in functionality over time. In

addition to operating at very high bandwidths, network

devices are being called upon to do more processing than

the standard protocols. Implementations of these

functions often have to change; for example, as service

parameters change for quality of service implementations

and new algorithms or techniques are developed for security applications. Software-based network devices provide a programmable base to support these advanced and changing functions, but they are unable in most cases to support very high data rates [3, 4]. Current research generally uses one of two technologies to perform network processing at high bandwidths. Software-based implementations often use a network processor, such as the Intel IXP1200, to implement the required functionality. Alternatively, some researchers focus development of reprogrammable hardware-based systems that utilize Field Programmable Gate Arrays (FPGAs). Researchers have investigated other technologies, however network processors and FPGAs are the predominant implementation devices. A review of current work and an overview of the project described in this paper are provided in the next two subsections. Sections 2 and 3 describe the architecture of the CiNIC presented in this paper and conclusions are provided in Section 4. 1.1 Current Work

At least two research groups, one from Georgia Institute of Technology and another from Princeton University, have used Intel IXP network processors for research projects. The authors in [5] describe a software programmable router that uses an Intel IXP1200 network processor and a PentiumIII general-purpose processor. Computational resources are logically divided into three functional layers with the lowest level (the IXP1200 MicroEngines) performing common data plane processing and the PentiumIII at the highest level performing control plane processing. The middle layer contains the StrongARM processor present in the IXP1200. Additionally, the authors in [4] describe an IXP1200-based network co-processor card used for traffic modification within a storage area network. Ut
ilizing the co-processor improved performance while using a lightweight messaging system. Other researchers have used reprogrammable hardware to perform the network processing. Moving the implementation from software to reprogrammable hardware provides system designers with a greater degree of flexibility, which allows many operations, such as

At least two research groups, one from Georgia Institute of Technology and another from Princeton University, have used Intel IXP network processors for research projects. The authors in [5] describe a software programmable router that uses an Intel IXP1200 network processor and a PentiumIII general-purpose processor. Computational resources are logically divided into three functional layers with the lowest level (the IXP1200 MicroEngines) performing common data plane processing and the PentiumIII at the highest level performing control plane processing. The middle layer contains the StrongARM processor present in the IXP1200. Additionally, the authors in [4] describe an IXP1200-based network co-processor card used for traffic modification within a storage area network. Utilizing the co-processor improved performance while using a lightweight messaging system. Other researchers have used reprogrammable hardware to perform the network processing. Moving the implementation from software to reprogrammable hardware provides system designers with a greater degree of flexibility, which allows many operations, such as

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